Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 173)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 173
Cell 339,343,347, ... match to the SBI interface 1 (PMC8310
chip 1), subsystem 3, channel 0,1,2,
...
The cells 672,673 ... unused
...
The cells 768,769, ... 771 match to the T1 interface 0 (Xrt86
framer chip 0) channel 0,1,2,3,
The cells 772,773, ... 775 match to the T1 interface 0 (Xrt86
framer chip 0) channel 4,5,6,7,
...
The cells 816,817 ... 1023 unused
0x50000
...
0x50FFF Gr8RcvDatMem0
...
Gr8RcvDatMem102
3 Gr8 Receive Data Memory (32bit)
Holds the receive data for 672 Gr8 via Sonet/Sdh and 48 Gr8
channels via Exar T1 Framers.
Is copied to host memory by means of host DMA in 9ms
intervalls, the host is triggered by interrupt (see General
Registers Component Event Register).
The actual memory has the double of the needed size, always
one half is visible to the SW during an interval, the other half is
accessed by HW. In the next interval the two memory halves
are interchanged, thus decoupling SW from HW ensuring
enough processing time for SW.
The cells contain the Receive Concentrator Field and Receive
Maintenance., Alarm, Protection Switch Fields of the channels.
The cells contain the Receive Concentrator Field and Receive
Maintenance., Alarm, Protection Switch Fields of the channels.
The cells 0...767 are prepared by Hw to receive data from
Pmc8310 Sonet/Sdh Framers. A respective Tsi connection is
needed for every used channel.
The cells 768...1023 are prepared by Hw to receive data from
Xrt86 Framers. The channels can only be used in groups of four.
All four channels must be switched by the Tsi to the respective
Hmvip link channel 0 of a E1/T1 framer (broadcast). The cells
contain the Transmit Concentrator Field and Transmit
Maintenance., Alarm, Protection Switch Fields of the channels.
They may be mapped as following:
The cells 0..335 match to the SBI interface 0 to PMC8310 chip
0, 336 to 671 or SBI interface 1 to PMC8310 chip 1.
Table 9-5 RTM FPGA Address map Overview (continued)