Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 152)

Base ARTM FPGA
ARTM-831X Installation and Use (6806800M76E) 152
8.5 Clocking Scheme
There is one main clock domain inside the FPGA. The clock domain is sourced by the Front
Board clock CLK and comprises the following logic blocks:
 CLK Master Clock from Front board
 All SPI Interfaced
 Reset controller
 Glue logic
 Telecom clocking interface
These entire logic blocks are running with the same clock at the same frequency. All signals
from other clock domains are synchronized to the CLK clock domain.
8.6 Logic Blocks
8.6.1 RTM SPI Interface
ARTM Base Register Accesses thru Glue Logic FPGA via RTM SPI Interface.
8.6.2 Mezzanine SPI Interface
The ARTM Mezzanine Card can access ARTM Base Registers via this SPI interface.
8.6.3 MMC I2C Slave Interface
The I2C Slave decodes accesses with slave address 0xFE. All other accesses are forwarded to the
selected SFP I2C Interface.