Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 70)

Functional Description
ARTM-831X Installation and Use (6806800M76E) 70
4.2.4 Synchronous Clock Functionality
All ARTM8310 resources except IPMC operate synchronous. The synchronous clocks are
generated by the system synchronizer device located on the front board. The ARTM-
831X_base uses the 25MHz basic IP reference clock to generate the required REFCLK signals for
the synchronous operating Ethernet Phys.
4.2.5 BITS Interfaces
Two BITS interface devices are available on the ARTM-831X base unit as an assembly option,
intended for use in variants that also employ a TDM mezzanine.
In the standard configuration BITS_1 is configured as T3 input clock and BITS_2 is a T4 clock
output. They are directly routed to the Front board system synchronizer via zone 3 connector.
Both BITS recovered receive clock are also available to the reference clock selector.
Transmit and receive side I/F are connected to the FPGA_base device to provide pattern
generation reception and E1 SSM reception.
4.2.6 OC3 option
The OC-3 option for ARTM-831XARTM-831X is an assembly option of the ARTM-831X_base
PCA. It is provided in combination with the ARTM-831X_DS3/OC3 mezzanine expansion PCA.
The SDH/Sonet Framer device is located on the mezzanine, while the SFP Transceiver devices
reside on the base board. The Rx/Tx signals are routed via the mezzanine connector. The SFP
overhead signals are routed to the FPGA_base device.