Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 285)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 285
Table 9-12 PCI Class Code
PCI Configuration Offset: 0x09
Bit Description Default Access
7:0 Specific register level programming interface (not defined) 0 PCI: r
15:8 Sub class encoding (other bridge device) 0x80 PCI: r
23:16 Base class encoding (other bridge device) 0x06 PCI: r
Table 9-13 PCI Header Type
PCI Configuration Offset: 0x0E
Bit Description Default Access
6:0 Device has Type 0 Configuration Space Header layout. 0 PCI: r
7 Single function device 0 PCI: r
Table 9-14 PCI Base Address Register 0
PCI Configuration Offset: 0x10
Bit Description Default Access
0 Memory Space indicator. 0 PCI: r
2:1 Locate anywhere in 32 bit memory address space. 0 PCI: r
3 Address range is pre-fetchable. (No side effects on read). 1 PCI: r
23:4 Hardcoded 0 PCI: r
31:24 Base Address used to map 16 MB into PCI memory space. PCI_RST_: 0xFF PCI: r/w
Table 9-15 PCI Base Address Register 1
PCI Configuration Offset: 0x14
Bit Description Default Access
0 IO Space indicator 1 PCI: r
10:1 Hardcoded 0 PCI: r