Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 221)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 221
The Serdes transmitter status is shown.
Reg0 is for Serdes-connection to the BaseBoard, Reg1 to DMC1 and Reg2 to DMC2.
9.5.2.9.3 Supplemental Test Pattern Receive Data Register
Addresses:
0x1202, SupplTstPatDataRcvDatReg0
0x1242, SupplTstPatDataRcvDatReg1
0x1282, SupplTstPatDataRcvDatReg2
Width: 16 bit
This register provides the received test pattern from the supplementary channel.
Bit Acronym Type
Description
Default
Pwr Soft
7 SerdesRcvPllLolFlag R 0b1: SerdesRcvPllLolFlag, Set when the
Serdes receiver PLL has lost lock. Reset
by respective bit in SerDesTrmCtrlReg 0b0 F F
6 SerdesRcvLosFlag R 0b1: SerdesRcvLosFlag, set when the
loss of signal 0b0 F F
5 SerdesRcvHasFound
CommaFlag R 0b1: SerdesRcvHasFoundCommaFlag,
set when first comma found, after
period with no commas. 0b0 F F
4 - - reserved undef - -
3 SerdesRcvPllLol R 0b1: SerdesRcvPllLol, Shows actual
status of Serdes receiver PLL lock. 0b0 F F
2 SerdesRcvLos R 0b1: SerdesRcvLos, current the loss of
signal status 0b0 F F
1 SerdesRcvHasFound
Comma R 0b1: SerdesRcvHasFoundComma,
current status of comma detection 0b0 F F
0 - - reserved 0b0 F F