Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 160)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 160
 Spi-interface to program the configuration prom of the FPGA and to force the boot of
golden image.
 Control and status registers for all interfaces.
 Base Board identifier.
 Fpga Version and matching ExtFpga subset version register.
 FPGA Frame synchronisation with 8kHz frame sync and 166Hz extended super frame sync.
 16.384 MHz clock generation for 6 HMVIP interfaces of E1/T1 framers.
 8 kHz frame sync generation for 6 HMVIP interfaces of E1/T1 framers.
 Programmable multi frame sync generation for E1/T1 framers.
 8 kHz frame sync generation for SBI add interface SONET/SDH-framers
 Multi frame sync generation for SONET/SDH-framers.
 Transmit of partner multi frame sync pulse via path overhead of Sonet/SDH framers or to
LVDS buffer. Receive of partner multi frame sync pulse via path overhead of Sonet/SDH
framers or from LVDS buffer and determination of offset.
 Fully synchronous design with three major clock domains (77.76MHz, 131.072 MHz, and
125 MHz).
12.288 Mhz clock buffer for line interface unit clocks.
9.2 Device Specifics
9.2.1 FPGA Device Type
Table 9-1 FPGA Device Type
Characteristic Value
Vendor Lattice
Device Family ECP2M