Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 269)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 269
This register monitor the loss of signal outputs of the Pmc8310 framer chips 0,1and the Xrt86
framer chips 0,1. If a loss of signal occurs, the respective bit is set. It can be reset by writing the
respective bit in Xrt86LineEvtResReg.
Bit Acronym Type Description Default Pwr Soft
31...24 - - reserved undef - -
23 Pmc83Chp1RcvLoS3 R 0b1:
Pmc83Chp1RcvLoS3,
Chip 1 receiver Line 3
indicates loss of signal 0b0 F F
22 Pmc83Chp1RcvLoS2 R 0b1:
Pmc83Chp1RcvLoS2,
Chip 1 receiver Line 2
indicates loss of signal 0b0 F F
21 Pmc83Chp1RcvLoS1 R 0b1:
Pmc83Chp1RcvLoS1,
Chip 1 receiver Line 1
indicates loss of signal 0b0 F F
20 Pmc83Chp1RcvLoS0 R 0b1:
Pmc83Chp1RcvLoS0,
Chip 1 receiver Line 0
indicates loss of signal 0b0 F F
19 Pmc83Chp0RcvLoS3 R 0b1:
Pmc83Chp0RcvLoS3,
Chip0 receiver Line 3
indicates loss of signal 0b0 F F
18 Pmc83Chp0RcvLoS2 R 0b1:
Pmc83Chp0RcvLoS2,
Chip0 receiver Line 2
indicates loss of signal 0b0 F F
17 Pmc83Chp0RcvLoS1 R 0b1:
Pmc83Chp0RcvLoS1,
Chip0 receiver Line 1
indicates loss of signal 0b0 F F
16 Pmc83Chp0RcvLoS0 R 0b1:
Pmc83Chp0RcvLoS0,
Chip0 receiver Line 0
indicates loss of signal 0b0 F F