Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 158)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 158
9.1.1 Unit Description
The main task of the TSI-FPGA is to provide a 65536 channel timeslot interchanger (TSI) to
connect the speech payload of up to 3 DSP-modules via 2.5 Gbit/s SERDES links, 2 PM8310
SONET/SDH-framers via SBI links and Transport Overhead links and up to 6 Octal E1/T1-
framers via HMVIP-links.
Another major task is the generation and processing of GR08 signaling.
The TSI-FPGA is controlled by a host processor via a PCI-Express (x1) interface. It bridges this
bus to a 16/8bit local bus to allow the control of 8 line interface units and 2 SONET/SDH-
framers.
It bridges it further to a SPI-interface to control other components outside the FPGA, e.g. a Bits-
clock-element.
It provides an additional SPI-interface which is connected to an I/O-Extender PLD. The
sideband signals of the framers and other components are connected to this PLD and are
imaged automatically between the TSI-FPGA and the PLD.
Interrupts signals of the framers and other components are sent backwards to the host by
message based interrupts through the PCI-Express interface.