Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 87)

Functional Description
ARTM-831X Installation and Use (6806800M76E) 87
E1/T1 Framer:
 Receive Loss of signal (FPGA input)
 Receive Termination Control (FPGA I/O)
 Transmitter ON (FPGA I/O)
DS3 LIU:
 Receive Loss of signal (FPGA input)
 Receive Loss of Lock (FPGA input)
 Drive Monitor Output (FPGA input)
SONET/SDH Framer:
 Receive Working Loss of signal (FPGA input)
4.4.2.4 Register Description
For details, see Chapter 10, EXT FPGA, on page 293
4.4.3 PM8310 TEMUX336 SDH/Sonet Framer
Two TEMUX336 devices provide a total of 8 OC-3 interfaces (optionally 2x OC12) or 24 E3/DS3
interfaces via the following connectivity:
4.4.3.1 SBI336 Interface
Both TEMUX336 devices are connected to the TSI-FPGA via their own Scalable Bandwidth
Interconnect (SBI336) bus. SBI336 is a Telecom bus style interface that pin-efficiently transfers
up to 336 T1 or 252 E1, 12 DS3 or 12 E3, or 12 SPEs, containing transparent virtual tributaries
or arbitrary bandwidth payloads. The buses are timed to a 77.76MHz common reference clock
and a 166.7Hz multi frame alignment and synchronization pulse is used.
4.4.3.2 Local Bus
The TEMUX336 devices are connected to the TSI-FPGA Local Bus Interface in asynchronous,
non-multiplexed, Intel bus mode. The address bus width is 16bit. The data bus width is 16bit.
Data word aligned access is controlled by the TSI_FPGA.