Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 276)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 276
15 Xrt86Chp1RcvLoSIntrpt
Mask7 RW 0b1:
Xrt86Chp1RcvLoSIntrptEnabl
e7, enables chip1 receiver Line
7 loss of signal interrupt bit 0b0 X X
14 Xrt86Chp1RcvLoSIntrpt
Mask6 RW 0b1:
Xrt86Chp1RcvLoSIntrptEnabl
e6, enables chip1 receiver Line
6 loss of signal interrupt bit 0b0 X X
13 Xrt86Chp1RcvLoSIntrpt
Mask5 RW 0b1:
Xrt86Chp1RcvLoSIntrptEnabl
e5, enables chip1 receiver Line
5 loss of signal interrupt bit 0b0 X X
12 Xrt86Chp1RcvLoSIntrpt
Mask4 RW 0b1:
Xrt86Chp1RcvLoSIntrptEnabl
e4, enables chip1 receiver Line
4 loss of signal interrupt bit 0b0 X X
11 Xrt86Chp1RcvLoSIntrpt
Mask3 RW 0b1:
Xrt86Chp1RcvLoSIntrptEnabl
e3, enables chip1 receiver Line
3 loss of signal interrupt bit 0b0 X X
10 Xrt86Chp1RcvLoSIntrpt
Mask2 RW 0b1:
Xrt86Chp1RcvLoSIntrptEnabl
e2, enables chip1 receiver Line
2 loss of signal interrupt bit 0b0 X X
9 Xrt86Chp1RcvLoSIntrpt
Mask1 RW 0b1:
Xrt86Chp1RcvLoSIntrptEnabl
e1, enables chip1 receiver Line
1 loss of signal interrupt bit 0b0 X X
8 Xrt86Chp1RcvLoSIntrpt
Mask0 RW 0b1:
Xrt86Chp1RcvLoSIntrptEnabl
e0, enables chip1 receiver Line
0 loss of signal interrupt bit 0b0 X X
7 Xrt86Chp0RcvLoSIntrpt
Mask7 RW 0b1:
Xrt86Chp0RcvLoSIntrptEnabl
e7, enables chip 0 receiver Line
7 loss of signal interrupt bit 0b0 X X
Bit Acronym Type Description Default Pwr Soft