Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 319)

EXT FPGA
ARTM-831X Installation and Use (6806800M76E) 319
10.4.2.1.12Xrt75 Line Interface Line Event Reset Register
Addresses:
0x34, Xrt75LineEvtResReg0
0x44, Xrt75LineEvtResReg1
0x54, Xrt75LineEvtResReg2
0x64, Xrt75LineEvtResReg3
Width: 32 bit
11 Xrt75RcvLoL3 R 0b1: Xrt75RcvLostLock3, Receiver
Line 3 indicates loss of lock 0b0 F F
10 Xrt75RcvLoL2 R 0b1: Xrt75RcvLostLock2, Receiver
Line 2 indicates loss of lock 0b0 F F
9 Xrt75RcvLoL1 R 0b1: Xrt75RcvLostLock1, Receiver
Line 1 indicates loss of lock 0b0 F F
8 Xrt75RcvLoL0 R 0b1: Xrt75RcvLostLock0, Receiver
Line 0 indicates loss of lock 0b0 F F
7...6 - - reserved undef - -
5 Xrt75RcvLoS5 R 0b1: Xrt75RcvLostSig5, Receiver Line
5 indicates loss of signal 0b0 F F
4 Xrt75RcvLoS4 R 0b1: Xrt75RcvLostSig4, Receiver Line
4 indicates loss of signal 0b0 F F
3 Xrt75RcvLoS3 R 0b1: Xrt75RcvLostSig3, Receiver Line
3 indicates loss of signal 0b0 F F
2 Xrt75RcvLoS2 R 0b1: Xrt75RcvLostSig2, Receiver Line
2 indicates loss of signal 0b0 F F
1 Xrt75RcvLoS1 R 0b1: Xrt75RcvLostSig1, Receiver Line
1 indicates loss of signal 0b0 F F
0 Xrt75RcvLoS0 R 0b1: Xrt75RcvLostSig0, Receiver Line
0 indicates loss of signal 0b0 F F
Bit Acronym Type Description Default Pwr Soft