Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 183)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 183
0x1300
0x1304
0x1308
0x130C
0x1320
0x1324
0x1328
0x132C TohCtrReg00
TohCtrReg01
TohCtrReg02
TohCtrReg03
TohCtrReg10
TohCtrReg11
TohCtrReg12
TohCtrReg13 Transport Overhead Control Register (32bit) [Hw: asyn,
WAck5, RAck5]
The RtmFpga connects to 2 Sonet/Sdh-framers. Each framer
may connect to 4 STM1/OC3 data streams, each containing
E1,2 and D1..12 DCCbytes in similar fashion.
This results in a total of 8 registers to enable the insertion of
data from respective TSI channels by the framer at its add
interface.
0x1340
0x1344
0x1348
0x134C
0x1360
0x1364
0x1368
0x136C TohStatReg00
TohStatReg01
TohStatReg02
TohStatReg03
TohStatReg10
TohStatReg11
TohStatReg12
TohStatReg13 Transport Overhead Status Register (32bit) [Hw: asyn, WAck5,
RAck5]
The RtmFpga connects to 2 Sonet/Sdh-framers. Each framer
may connect to 4 STM1/OC3 data streams, each containing
E1,2 and D1..12 DCCbytes in similar fashion.
This results in a total of 8 registers to notice wether valid data is
sent by the framer from its drop interface to respective TSI
channels or not.
General Register (GnrlRegs) [Hw: Cy1, InR, OutR]
Collection of general register not dedicated to particular functions
Access via PCI-bus 512kByte non-prefetchable memory area of 64bit-bar[3,2], hereof assigned to this
block: 1400...14FF
Address Acronym Description
0x1400 SoftResReg Soft Reset Register (32bit) [Hw: syn, WAck1, RAck1, WTP]
Brings by SoftReset affected registers to power up state
0x1404 RtmFpgaVerReg RtmFpga Version Register (32bit) [Hw: syn, WAck1, RAck1]
The version of the RtmFpga determined by compilation is read.
0x1408 RtmMatchExtFpgaV
erReg Matching ExtFpga Version Register (32bit) [Hw: syn, WAck1,
RAck1]
The version of the matching ExtFpga (since ExtFpga extends
RtmFpga) is read. Must match always exactly the version in
RtmMatchExtFpgaVerReg within ExtFpga determined by
compilation
Table 9-5 RTM FPGA Address map Overview (continued)