Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 225)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 225
Reg0 is for Serdes-connection to the BaseBoard, Reg1 to DMC1 and Reg2 to DMC2.
9.5.2.9.8 Deserializer CRC Error Count Register
Addresses:
0x1210, CrcErrCntReg0
0x1250, CrcErrCntReg1
0x1290, CrcErrCntReg2
Width: 32 bit
This register indicates the number of the CRC errors since enabling the CRC error counting by
the ErrCntCtrlReg:CrcErrCntStart bit. The error counter sticks at 0xFFFFFF.
Reg0 is for Serdes-connection to the BaseBoard, Reg1 to DMC1 and Reg2 to DMC2.
9.5.2.9.9 Deserializer Disparity Error Count Register
Addresses:
0x1214, DispErrCntReg0
Bit Acronym Type
Description
Default
Pwr Soft
31..
.24 - - reserved undef - -
23..
.0 SupplTstPatErrCnt R This register indicates the number of
erroneous pattern. The error counter
sticks at 0xFFFFFF. 0x0 F F
Bit Acronym Type
Description
Default
Pwr Soft
31..
.24 - - reserved undef - -
23..
.0 CrcErrCnt R This register indicates the number of
frames with erroneous CRC. The error
counter sticks at 0xFFFFFF 0x0 F F