Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 273)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 273
15 Xrt86Chp1RcvLoSReset7 RW 0b1:
Xrt86Chp1RcvLoSReset7,
resets chip1 receiver Line 7
loss of signal indicator bit 0b0 X X
14 Xrt86Chp1RcvLoSReset6 RW 0b1:
Xrt86Chp1RcvLoSReset6,
resets chip1 receiver Line 6
loss of signal indicator bit 0b0 X X
13 Xrt86Chp1RcvLoSReset5 RW 0b1:
Xrt86Chp1RcvLoSReset5,
resets chip1 receiver Line 5
loss of signal indicator bit 0b0 X X
12 Xrt86Chp1RcvLoSReset4 RW 0b1:
Xrt86Chp1RcvLoSReset4,
resets chip1 receiver Line 4
loss of signal indicator bit 0b0 X X
11 Xrt86Chp1RcvLoSReset3 RW 0b1:
Xrt86Chp1RcvLoSReset3,
resets chip1 receiver Line 3
loss of signal indicator bit 0b0 X X
10 Xrt86Chp1RcvLoSReset2 RW 0b1:
Xrt86Chp1RcvLoSReset2,
resets chip1 receiver Line 2
loss of signal indicator bit 0b0 X X
9 Xrt86Chp1RcvLoSReset1 RW 0b1:
Xrt86Chp1RcvLoSReset1,
resets chip1 receiver Line 1
loss of signal indicator bit 0b0 X X
8 Xrt86Chp1RcvLoSReset0 RW 0b1:
Xrt86Chp1RcvLoSReset0,
resets chip1 receiver Line 0
loss of signal indicator bit 0b0 X X
7 Xrt86Chp0RcvLoSReset7 RW 0b1:
Xrt86Chp0RcvLoSReset7,
resets chip 0 receiver Line 7
loss of signal indicator bit 0b0 X X
Bit Acronym Type Description Default Pwr Soft