Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 228)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 228
9.5.2.10.2 Transport Overhead Status Register
Addresses:
0x1340, TohStatReg00
0x1344, TohStatReg01
0x1348, TohStatReg02
0x134C, TohStatReg03
0x1360, TohStatReg10
0x1364, TohStatReg11
0x1368, TohStatReg12
0x136C, TohStatReg13
Width: 32 bit
The RtmFpga connects to 2 Sonet/Sdh-framers. Each framer may connect to 4 STM1/OC3 data
streams, each containing E1,2 and D1..12 DCCbytes in similar fashion.
4 EnD5 RW 0b1: EnD5, enables the insertion of
channel data from TSI into D5 0b0 X X
3 EnD4 RW 0b1: EnD4, enables the insertion of
channel data from TSI into D4 0b0 X X
2 EnD3 RW 0b1: EnD3, enables the insertion of
channel data from TSI into D3 0b0 X X
1 EnD2 RW 0b1: EnD2, enables the insertion of
channel data from TSI into D2 0b0 X X
0 EnD1 RW 0b1: EnD1, enables the insertion of
channel data from TSI into D1 0b0 X X
Bit Acronym Type
Description
Default
Pwr Soft