Tsi fpga – Artesyn ARTM-831X Installation and Use (June 2014) User Manual
Page 217
TSI FPGA
ARTM-831X Installation and Use (6806800M76E)
217
0x1101, SerDesTrmStatReg0
0x1141, SerDesTrmStatReg1
0x1181, SerDesTrmStatReg2
Width: 8 bit
The Serdes transmitter status is shown.
Reg0 is for Serdes-connection to the BaseBoard, Reg1 to DMC1 and Reg2 to DMC2.
9.5.2.8.3 Supplemental Test Pattern Transmit Register
Addresses:
0x1102, SupplTstPatTrmReg0
0x1142, SupplTstPatTrmReg1
0x1182, SupplTstPatTrmReg2
Width: 16 bit
Static Test Pattern transmitted via the supplementary channel towards the serial interface.
Bit
Acronym
Type
Description
Default
Pwr
Soft
7
SerdesTrmPllLolFlag
R
0b1: SerdesTrmPllLolFlag, Set when the
Serdes transmitter PLL has lost lock.
Reset by respective bit in
SerDesTrmCtrlReg
0b0
F
F
6...
4
-
-
reserved
undef
-
-
3
SerdesTrmPllLol
R
0b1: SerdesTrmPllLol, Shows actual
status of Serdes transmitter PLL lock.
0b0
F
F
2...
0
-
-
reserved
undef
-
-
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