Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 306)

EXT FPGA
ARTM-831X Installation and Use (6806800M76E) 306
The bits of this register reset the respective bits in CompEvtReg. Writing a 1 to a bit in
CompEvtResReg resets the corresponding bit in CompEvtReg. The interrupt bit in CompEvtReg
is kept reset until writing a 0 to the corresponding bit in CompEvtResReg re-enables its monitor
function again.
10.4.2.1.7 Component Event Status Mask Register
Address:
0x18, CompEvtMaskReg
Width: 8 bit
Bit Acronym Type Description Default Pwr Soft
7...5 - - reserved undef - -
4 Xrt86FramerAlrmReset RW 0b1: Xrt86FramerAlrmReset,
resets CompEvtReg Xrt86
framer alarm bit 0b0 X X
3 Xrt75LiuAlrmReset1 RW 0b1: Xrt75LiuAlrmReset1,
resets CompEvtReg bit
Xrt75LiuAlrm1 0b0 X X
2 Xrt75LiuAlrmReset0 RW 0b1: Xrt75LiuAlrmReset0,
resets CompEvtReg bit
Xrt75LiuAlrm0 0b0 X X
1 Xrt75LiuAlrmReset-1 RW 0b1: Xrt75LiuAlrmReset-1,
resets CompEvtReg bit
Xrt75LiuAlrm-1 0b0 X X
0 Xrt75LiuAlrmReset-2 RW 0b1: Xrt75LiuAlrmReset-2,
resets CompEvtReg bit
Xrt75LiuAlrm-2 0b0 X X