Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 266)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 266
All clocks except the E1T1 clocks from the sonet framers are gated with their respective LoS
signal.
Bit Acronym Type Description Default Pwr Soft
31...26 - - reserved undef - -
25...24 SrcBlkRLclkSel RW 0b00: Pmc83BlkSel, Select
clock from Pmc83 block
0b01: Xrt86BlkSel, Select clock
from Xrt86 block
0b10: reserved
0b11: reserved 0b00 X X
23...22 - - reserved undef - -
21...20 Pmc8310OutChipSel RW 0b00: Pmc83OutSdhChip0Sel,
Select framer Sdh recovered
line clock output (a PgrmRclk)
from chip 0
0b01: Pmc83OutSdhChip1Sel,
Select framer Sdh recovered
line clock output (a PgrmRclk)
from chip 1
0b10:
Pmc83OutE1T1Chip0Sel,
Select framer E1T1 recovered
line clock output (a RecvClk)
from chip 0
0b11:
Pmc83OuttE1T1Chip1Sel,
Select framer E1T1 recovered
line clock output (a RecvClk)
from chip 1 0b00 X X
19...18 - - reserved undef - -