Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 154)

Base ARTM FPGA
ARTM-831X Installation and Use (6806800M76E) 154
8.6.4 Shared Registers
Some registers are accessible from Mezzanine, Front Board and MMC. See Table "ARTM Base
FPGA Register Overview" on page 129 .
8.6.5 IP Only Registers
The IP registers are only accessible from Front Board.
8.6.6 TDM Only Registers
The TDM only registers are only accessible from Mezzanine card.
8.6.7 Hardware Protection
In the project some of the used FPGA are identical. During debugging it is possible, that a FPGA
is configured unintended with a wrong bitstream. Because each pinning of the FPGA devices is
different, signal contention may occur and may damage devices.
8.6.8 ARTM Base FPGA Configuration Supervision
The Soft Error Detect (SED) implementation is similar to the Glue Logic FPGA implementation.
8.6.9 ARTM Base FPGA Dual Configuration
A standard SPI flash device is used to store Golden and Working bitstream.
The Lattice device supports dual configuration images. The configuration mode is called SPIm.
(CFG[2:0]= 0b010).
The SPI write protection configuration is frozen, when the SPI Flash pin WP# is pulled down and
SPRL bit of the SPI Flash is set. When the SPRL bit is not set SW is allowed to reprogram of the
"Golden" bitstream image.
The Lattice devices don't support to force the device to load the Golden image. When the
Working image is valid the Working image will be loaded. With FPGA logic a feature is added
to force the device to load the Golden Image.