Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 250)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 250
The bits of this register mask the bits of the CompEvtReg. for the generation of a Interrupt (MSI)
to the host via PCIE.
Bit Acronym Type Description Default Pwr Soft
31 Gr8IntrptMask RW 0b1: Gr8IntrptEnable, enables
CompEvtReg Gr8Intrpt 0b0 X X
30 Spi2IntrptMask RW 0b1: Spi2IntrptEnable, enables
the Spi bus 2 (from BaseExtFpga)
interrupt 0b0 X X
29 Spi1IntrptMask RW 0b1: Spi1IntrptEnable, enables
the Spi bus 1 (from ExtFpga)
interrupt 0b0 X X
28...12 - - reserved undef - -
11 Xrt75ChpIntrptMask3 RW 0b1: Xrt75ChpIntrptEnable3,
enables CompEvtReg
IntrptXrt75_3 0b0 X X
10 Xrt75ChpIntrptMask2 RW 0b1: Xrt75ChpIntrptEnable2,
enables CompEvtReg
IntrptXrt75_2 0b0 X X
9 Xrt75ChpIntrptMask1 RW 0b1: Xrt75ChpIntrptEnable1,
enables CompEvtReg
IntrptXrt75_1 0b0 X X
8 Xrt75ChpIntrptMask0 RW 0b1: Xrt75ChpIntrptEnable0,
enables CompEvtReg
IntrptXrt75_0 0b0 X X
7 Xrt86ChpIntrptMask5 RW 0b1: Xrt86ChpIntrptEnable5,
enables CompEvtReg
IntrptXrt86_5 0b0 X X
6 Xrt86ChpIntrptMask4 RW 0b1: Xrt86ChpIntrptEnable4,
enables CompEvtReg
IntrptXrt86_4 0b0 X X
5 Xrt86ChpIntrptMask3 RW 0b1: Xrt86ChpIntrptEnable3,
enables CompEvtReg
IntrptXrt86_3 0b0 X X
4 Xrt86ChpIntrptMask2 RW 0b1: Xrt86ChpIntrptEnable2,
enables CompEvtReg
IntrptXrt86_2 0b0 X X