Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 235)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 235
9.5.2.11.7 Synchronisation and Error Monitor Reset Register
Address:
0x141C, SyncErrMonResReg
Width: 32 bit
The bits of this register reset the respective bits in SyncErrMonReg. Writing a 1 to a bit resets
the corresponding bit in SyncErrMonReg. The corresponding bit is kept reset until writing a 0
re-enables its monitor function again.
3 NoTdmEsfSync R 0b1: NoTdmEsfSync, no main
extended superframe 166.66Hz sync
pulse from TDM system clock
generator undef - -
2 NoMainTdmFrameSy
nc R 0b1: NoMainTdmFrameSync, no main
frame sync 8kHz pulse from TDM
system clock generator undef - -
1 NoMainClkPllLock77 R 0b1: NoMainClkPllLock77, main clock
77.76MHz PLL not locked to TDM
system clock undef - -
0 NoMainClkPllLock13
1 R 0b1: NoMainClkPllLock131, main clock
131.072MHz PLL not locked to TDM
system clock undef - -
Bit Acronym Type
Description
Default
Pwr Soft
Bit Acronym Type
Description
Default
Pwr Soft
31 SerdesCltIfIntrptRes3 RW 0b1: SerdesCltIfIntrptRes3, reset
Interrupt from Serdes Quad3 indicator 0b0 X X
30 SerdesCltIfIntrptRes2 RW 0b1: SerdesCltIfIntrptRes2, reset
Interrupt from Serdes Quad2 indicator 0b0 X X
29 SerdesCltIfIntrptRes1 RW 0b1: SerdesCltIfIntrptRes1, reset
Interrupt from Serdes Quad1 indicator 0b0 X X
28 SerdesCltIfIntrptRes0 RW 0b1: SerdesCltIfIntrptRes0, reset
Interrupt from Serdes Quad0 indicator 0b0 X X