Tsi fpga – Artesyn ARTM-831X Installation and Use (June 2014) User Manual
Page 212
TSI FPGA
ARTM-831X Installation and Use (6806800M76E)
212
9.5.2.7.2 Test Pattern Comparator Receive Data Register
Addresses:
0x10C2, TstPatRcvDatReg0
0x10E2, TstPatRcvDatReg1
Width: 8 bit
This registers holds the received pattern in the case of static pattern reception. Not used in the
case of pseudo random pattern reception.
9.5.2.7.3 Test Pattern Comparator Data Register
Addresses:
0x10C3, TstPatCmpDatReg0
0x10E3, TstPatCmpDatReg1
Width: 8 bit
This registers holds the reference pattern in the case of static pattern reception. Not used in the
case of pseudo random pattern reception.
9.5.2.7.4 Test Pattern Comparator Control Register
Addresses:
0x10C4, TstPatCmpCtrlReg0
Bit
Acronym
Type
Description
Default
Pwr
Soft
7...
0
StatRcvdPatData
R
Received pattern for the static pattern
reception.
0x0
X
X
Bit
Acronym
Type
Description
Default
Pwr
Soft
7...
0
RcvCmpPatData
RW
Compare pattern for the static pattern
reception.
0x0
X
X
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