Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 295)

EXT FPGA
ARTM-831X Installation and Use (6806800M76E) 295
10.3 Logic Blocks
10.3.1 SPI Interface
The SPI interface connects ExtFPGA to the TSI-FPGA to realize the remote parallel I/O
expansion. Via the SPI the TSI-FPGA continuously reads status information from and writes
control information to the remote parallel I/O expansion. The content of status and control
information is accessible to the back end Wishbone bus of the TSI-FPGA.
10.3.2 Debug LEDs
The DSP FPGA drives a set of eight LEDs for status notification and debug purposes. The
meaning of the LEDs is defined as follows:
Table 10-3 Ext FPGA debug LEDs
Power / Reset indication
DebugLed[7] DebugLed[6]
On Off device loaded
ON:Off 1:1 ON:Off 1:1 LED 7/6 alternate blink for
normal operation
Serdes link to TSI FPGA indication
DebugLed[5:0] DebugLedReg Bit 5..0 =
101010 static