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Tsi fpga – Artesyn ARTM-831X Installation and Use (June 2014) User Manual

Page 271

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TSI FPGA

ARTM-831X Installation and Use (6806800M76E)

271

9.5.2.13.3 Pmc83 and Xrt86 Framer Line Event Status Reset Register

Address:

0x1614, Pmc83Xrt86LineEvtResReg

Width: 32 bit

3

Xrt86Chp0RcvLoS3

R

0b1: Xrt86Chp0RcvLoS3,
Chip 2 receiver Line 3
indicates loss of signal

0b0

F

F

2

Xrt86Chp0RcvLoS2

R

0b1: Xrt86Chp0RcvLoS2,
Chip 2 receiver Line 2
indicates loss of signal

0b0

F

F

1

Xrt86Chp0RcvLoS1

R

0b1: Xrt86Chp0RcvLoS1,
Chip 2 receiver Line 1
indicates loss of signal

0b0

F

F

0

Xrt86Chp0RcvLoS0

R

0b1: Xrt86Chp0RcvLoS0,
Chip 2 receiver Line 0
indicates loss of signal

0b0

F

F

Bit

Acronym

Type

Description

Default

Pwr

Soft