Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 197)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 197
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The cells 672,673 ... unused
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The cells 768,769, ... 771 match to the T1 interface 0 (Xrt86 framer chip 0) channel 0,1,2,3,
The cells 772,773, ... 775 match to the T1 interface 0 (Xrt86 framer chip 0) channel 4,5,6,7,
...
The cells 816,817 ... 1023 unused
Bit Acronym Type
Description
Default
Pwr Soft
31 Gr8TrmEn RW 0b1: Gr8TrmEnabled, The transmitter
of the channel is enabled. undef - -
30 Gr8FrmFltInsrtOn RW 0b1: Gr8FrmFltInsrtOn, Insert error in
FT bit sequence undef - -
29 Gr8TrmFltInsrtOn RW 0b1: Gr8TrmFltInsrtOff, Insert no
error in first or last 8 fixed bits of Gr8
frame
0b1: Gr8TrmFltInsrtOn, Insert error in
first or last 8 fixed bits of Gr8 frame undef - -
28 Gr8TrmFltInsrtInLast8 RW 0b0: Gr8TrmFltInsrtInFirst8, Insert
error in first 8 fixed bits of Gr8 frame
0b1: Gr8TrmFltInsrtInLast8, Insert
error in last 8 fixed bits of Gr8 frame undef - -
27..
.20 Gr8TrmFltInsrtBits RW Bits replacing first or last 8 fixed bits of
Gr8 frame if Gr8TrmFltInsrtOn is on undef - -