Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 77)

Functional Description
ARTM-831X Installation and Use (6806800M76E) 77
The SerDes lanes are operating at 2.5Gbit/s and provide a capacity of 60 512 channels.
The SerDes I/F is routed to the front board via the upper mezzanine connector and the zone 3
connector on the ARTM-831X base unit.
4.3.1.5 Register Description
For details, see Chapter 9, TSI FPGA, on page 157
4.3.2 TSI-Extender FPGA
The TSI- Extender FPGA device acts as a companion device for the TSI- FPGA. It is mainly used
as a pin- extender for the TSI-FPGA, to reduce its size and thus optimize board space utilization
and cost.
 Controlled from Host via SPI through the TSI FPGA
 Collects the recovered receive clocks from the E1/T1 framer devices
 Pre-selector for any 2 receive clocks as reference clock input to the system synchronizer on
the front board.
 Collects status & alarm signals from the E1/T1 Framer
 Update/failback SPI configuration Flash in working/golden mode
4.3.2.1 SPI Interface
The TSI-Extender FPGA has two SPI interfaces in total (see Figure "ARTM-831X SPI Bus & RESET
Structure" on page 65 . The first one is the link to the TSI-FPGA. It provides transparent access
and control of the I/O expansion. The second one is used for configuration and connects to a
SPI Flash device.