Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 213)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 213
0x10E4, TstPatCmpCtrlReg1
Width: 8 bit
This registers enables either static or pseudo random pattern reception.
9.5.2.7.5 Test Pattern Synchronization Status Register
Addresses:
0x10C8, TstPatCmpSyncStaReg0
Bit Acronym Type
Description
Default
Pwr Soft
7...
4 - - reserved undef - -
3 TstPatCmpBitstInvert RW 0b1: TstPatCmpBitstrInvert, selects
that test pattern bitstream is received
inverted
0b0: TstPatCmpBitstrNotInvert, selects
that test pattern bitstream is received
not inverted 0b0 X X
2 - - reserved undef - -
1 TstPatCmpPatSel RW Specifies the destination for the
pattern reception:
0b1: TstPatCmpPrbs, selects the PRBS
Comparator
0b0: TstPatCmpStatic, selects the
static pattern receive register
0b0 X X
0 TstPatCmpRxPatEn RW 0b1: TstPatCmpRxPatEn, enables the
pattern reception. Error and frame
counters and the synchronization
status bit are cleared, when this bit
changes from 0 to 1.$$$CR A time of
125us delay has to be taken into
account, till the comparator has
stopped after resetting
TstPatCmpRxPatEn bit. 0b0 X X