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3 pci configuration space, 1 overview, Table 9-6 – Artesyn ARTM-831X Installation and Use (June 2014) User Manual

Page 281: Pci configuration space register overview, Tsi fpga

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TSI FPGA

ARTM-831X Installation and Use (6806800M76E)

281

9.5.2.18 External components accesses through RTM FPGA as bridge to local bus

(ExtBridgedComp)

The RTM Fpga bridges the PCI Bus to a 16/8 Bit local Bus. The microprocessor interfaces of upto
4x XRT75 (8bit bus), 6x XRT86(8bit bus) and 2x PMC8310(16bit-bus) components are
connected to this bus. The bus width is adapted automatically to the needs of the accessed
component.

9.5.3

PCI Configuration Space

9.5.3.1

Overview

Table 9-6 PCI Configuration Space Register Overview

Byte 3, Bit [31:24]

Byte 2, Bit [23:16]

Byte 1, Bit [15:8]

Byte 0, Bit [7:0]

Offset

PCI Device ID (Table 9)

PCI Vendor ID (Table 8)

0x00

PCI Status (Table 11)

PCI Command (Table 10)

0x04

PCI Class Code (Table 13)

PCI Revision ID
(Table 12)

0x08

Reserved

PCI Header Type (Table
14)

Reserved

Reserved

0x0C

PCI Base Address Register 0 (Table 15)

0x10

PCI Base Address Register 1(Table 16)

0x14

PCI Base Address Register 2 (Table 17)

0x18

Reserved

0x1C

Reserved

0x20

Reserved

0x24

Reserved

0x28

PCI Subsystem ID Register (Table 19)

PCI Subsystem Vendor Register (Table 18) 0x2C

Reserved

0x30