Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 120)

Base ARTM FPGA
ARTM-831X Installation and Use (6806800M76E) 120
8.2.7 Telecom Base Clock Receive Clocks
The MMC selects one of the clocks N8707_RCLK_P/M, CLK_REFCLK_1 or CLK_REFCLK_2. See
4.3.1.11 Telecom Reference Clock Selection.
8.2.8 Telecom Clocks
8.2.9 Status Sonet SFP
Table 8-7 Telecom Base Clock Receive Clocks
Signal Name Type Description
N8707_RCLK_P/M I Differential 10 GE receive clock RCLK
GE_RECCLK1 I GE Receive clock 1
GE_RECCLK2 I GE Receive clock 2
CLK_REFCLK_1 O Receive clock REFCLK 1 to Zone 3
CLK_REFCLK_2 O Receive clock REFCLK 2 to Zone 3
Table 8-8 Telecom Base Clock Receive Clocks
Signal Name Type Description
RTM_CLK_16MHZ I TDM 16MHz Clock from Zone 3
FPGA_CLK_T4_OUT I TDM T4 Clock from Zone3
CLK_T3_BITS O TDM T3 BITS Clock to Zone3
Table 8-9 Status Sonet SFP
Signal Name Type Description
FPGA_ACTIVE_RTM_OUT I Status Signal ADM
SFP_TXFAULT_1 I Status TMUX 1 TXFAULT 1