Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 331)

EXT FPGA
ARTM-831X Installation and Use (6806800M76E) 331
Register to control testmodes.
10.4.2.3.4 Test Read Val Register
Address:
0xAC, TestReadValReg
Width: 32 bit
Register to read data for Hw test purposes.
10.4.2.4 Framer and Line Interface Unit Sideband Signal Registers
(FrLiuSdBndRegs)
Resets:
Pwr = Power on reset
Soft = Soft reset
Registers to control further processing or monitor signals of XRT86-framers and XRT75 Line
interfaces.
10.4.2.4.1 SelectRcvrdLclk
Addresses:
Bit Acronym Type Description Default Pwr Soft
7 ChgnProtSchm RW 0b1: ChgnProtSchm, must always be set
to 0 0b0 X X
6 SkipProtInitSeq RW 0b1: SkipProtInitSeq, must always be set
to 0 0b0 X X
5 RstCfgIf RW 0b1: RstCfgIf, must always be set to 0 0b0 X X
4...0 - - reserved undef - -
Bit Acronym Type Description Default Pwr Soft
31...0 TestReadData R Read data for Hw test purposes undef - -