Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 264)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 264
Register to control test modes
9.5.2.12.5 Test Read Val Register
Address:
0x1510, TestReadValReg
Width: 32 bit
Register to read data for Hw test purposes
Bit Acronym Type Description Default Pwr Soft
7 ChgnProtSchm RW 0b1: ChgnProtSchm, must
always be set to 0 0b0 X X
6 SkipProtInitSeq RW 0b1: SkipProtInitSeq, must
always be set to 0 0b0 X X
5 RstCfgIf RW 0b1: RstCfgIf, must always be
set to 0 0b0 X X
4 PciFrsclBigEndianMode RW 0b1: PciFrsclBigEndianMode,
enables special freescale byte
swap for pcie 0b0 X -
3...
1 - - reserved undef - -
0 DspRxFrameSyncMode RW 0b1: SerDesLoopBack, Frame
sync of Dsp receiver is adjusted
to correspond with different
delay of serdes link in loopback
mode
0b0: SerDesNormal, Frame
sync of Dsp receiver is in normal
operation mode 0b0 X X
Bit Acronym Type Description Default Pwr Soft
31...0 TestReadData R Read data for Hw test
purposes undef - -