Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 272)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 272
The bits of this register reset the respective bits in Pmc83Xrt86LineEvtReg. Writing a 1 to a bit
in Xrt86LineEvtResReg resets the corresponding bit in Pmc83Xrt86LineEvtReg The interrupt
bit in Pmc83Xrt86LineEvtReg is kept reset until writing a 0 to the corresponding bit in
Pmc83Xrt86LineEvtResReg re-enables its monitor function.again.
Bit Acronym Type Description Default Pwr Soft
31...24 - - reserved undef - -
23 Pmc83Chp1RcvLoSReset3 RW 0b1:
Pmc83Chp1RcvLoSReset3,
resets chip1 receiver Line 3
loss of signal indicator bit 0b0 X X
22 Pmc83Chp1RcvLoSReset2 RW 0b1:
Pmc83Chp1RcvLoSReset2,
resets chip1 receiver Line 2
loss of signal indicator bit 0b0 X X
21 Pmc83Chp1RcvLoSReset1 RW 0b1:
Pmc83Chp1RcvLoSReset1,
resets chip1 receiver Line 1
loss of signal indicator bit 0b0 X X
20 Pmc83Chp1RcvLoSReset0 RW 0b1:
Pmc83Chp1RcvLoSReset0,
resets chip1 receiver Line 0
loss of signal indicator bit 0b0 X X
19 Pmc83Chp0RcvLoSReset3 RW 0b1:
Pmc83Chp0RcvLoSReset3,
resets chip0 receiver Line 3
loss of signal indicator bit 0b0 X X
18 Pmc83Chp0RcvLoSReset2 RW 0b1:
Pmc83Chp0RcvLoSReset2,
resets chip0 receiver Line 2
loss of signal indicator bit 0b0 X X
17 Pmc83Chp0RcvLoSReset1 RW 0b1:
Pmc83Chp0RcvLoSReset1,
resets chip0 receiver Line 1
loss of signal indicator bit 0b0 X X
16 Pmc83Chp0RcvLoSReset0 RW 0b1:
Pmc83Chp0RcvLoSReset0,
resets chip0 receiver Line 0
loss of signal indicator bit 0b0 X X