Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 229)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 229
This results in a total of 8 registers to notice wether valid data is sent by the framer from its drop
interface to respective TSI channels or not.
9.5.2.11 General Register (GnrlRegs)
Resets:
Pwr = Power on reset
Soft = Soft reset
Collection of general register not dedicated to particular functions
Bit Acronym Type
Description
Default
Pwr Soft
31..
.18 - - reserved undef - -
17 VldE2 R 0b1: VldE2, valid E2 0b0 F F
16 VldE1 R 0b1: VldE1, valid E1 0b0 F F
15..
.12 - - reserved undef - -
11 VldD12 R 0b1: VldD12, valid D12 0b0 F F
10 VldD11 R 0b1: VldD11, valid D11 0b0 F F
9 VldD10 R 0b1: VldD10, valid D10 0b0 F F
8 VldD9 R 0b1: VldD9, valid D9 0b0 F F
7 VldD8 R 0b1: VldD8, valid D8 0b0 F F
6 VldD7 R 0b1: VldD7, valid D7 0b0 F F
5 VldD6 R 0b1: VldD6, valid D6 0b0 F F
4 VldD5 R 0b1: VldD5, valid D5 0b0 F F
3 VldD4 R 0b1: VldD4, valid D4 0b0 F F
2 VldD3 R 0b1: VldD3, valid D3 0b0 F F
1 VldD2 R 0b1: VldD2, valid D2 0b0 F F
0 VldD1 R 0b1: VldD1, valid D1 0b0 F F