Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 145)

Base ARTM FPGA
ARTM-831X Installation and Use (6806800M76E) 145
8.3.1.23 ARTM Interrupt Group Status
8.3.1.24 Identification Register
Table 8-48 ARTM Interrupt Group Status
Address: 0x1C
Bit Description Default Access
0 One or more SFP TXFAULT signals has changed and the corresponding
interrupt enable bit are set 0 RTM: r
1 One or more SFP MOD_ABS signals has changed and the
corresponding interrupt enable bit are set 0 RTM: r
2 One or more 10 GE status bits 0 to 7 has changed and the
corresponding interrupt enable bit are set 0 RTM: r
3 One or more 10 GE status bits 8 to 15 has changed and the
corresponding interrupt enable bit are set 0 RTM: r
4 Interrupt from Telecom Clock supervision. At least one measurement
for the supervised clocks has finished.
See Table ARTM Telecom Clock Monitor Status Register 0 RTM: r
5 Interrupt from Telecom Clock supervision. At least one supervised
clock is out of range.
See Table Telecom Clock Monitor Out of Range Register 0 RTM: r
7:6 Reserved 0 r
Table 8-49 Identification Register
Address: 0x1D
Bit Description Default Access
3:0 Board Type Identification. Level of TYPE_ID[3:0] Ext. r
7:4 Board Functional Identification. Level of FUNCT_ID[3:0] Ext. r