Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 214)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 214
0x10E8, TstPatCmpSyncStaReg1
Width: 32 bit
This registers indicates the status of the receiver for static pattern or the PRBS bit stream.
Bit Acronym Type
Description
Default
Pwr Soft
31 TstPatCmpSync R 0b1: TstPatCmpSync, indicates that the
specified receiver is synchronized to
the specified static pattern or the PRBS
bit stream.
The bit shows the current
synchronization status "live". It is only
valid when the receiver is running, i.e.
TstPatCmpRxPatEn is set. 0b0 F F
30 TstPatCmpSyncLost R 0b1: TstPatCmpSyncLost, indicates
that the specified receiver has lost
synchronization after a first successful
synchronization to the specified static
pattern or the PRBS bit stream.
The bit keeps its status after the
receiver is stopped, thus showing its
value during the last measurement. It is
cleared, when TstPatCmpRxPatEn bit
changes from 0 to 1. i.e. the receiver is
re-enabled again. 0b0 F F
29..
.24 - - reserved undef - -
23..
.0 TstPatCmpSyncCnt R Time elapsed since measurement has
started after successful
synchronization (value x 125μs). The
counter sticks at 0xFFFFFF. The count
keeps its status after the receiver is
stopped, thus showing its value during
the last measurement.The count is
cleared, when TstPatCmpRxPatEn bit
changes from 0 to 1. i.e. the receiver is
re-enabled again. 0b0 F F