Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 86)

Functional Description
ARTM-831X Installation and Use (6806800M76E) 86
4.4.2.2 Clock selection
The DS3/OC3 mezzanine expansion unit provides a programmable reference clock selector
unit. The TSI-Extender FPGA device expands the capability of the clock selector of the TSI FPGA
device for the DS3 LIU 0 to 3. Two reference clocks out of 24 recovered receive clocks are pre-
selected and routed to the ARTM-831X base unit via the upper mezzanine connector. At the
ARTM-831X base unit they are connected to the clock selection unit in the FPGA-base device
and depending on its configuration forwarded to the system synchronizer located at the front
board. Each of the inputs is masked on respective LOS alarm.
4.4.2.3 Status/Control & Alarm Signals
The status/control and alarm signals from the E1/T1 Framer, and the SONET/SDH Framer are
routed to the TSI-FPGA device. Signals from the DS3 LIU are routed to the Ext-FPGA:
Figure 4-12 DS3/OC3 mezzanine recovered receive clock selector unit
TDM RefClk 2
TDM_RefClk_3
To
ba
se bo
ard
vi
a
upp
er me
zza
ni
ne
conn
ect
o
r
24x recovered receive CLK
from E3/DS3 LIU
Mask input on respective LOS Alarm
. . . . . . . .