Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 194)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 194
Pwr = Power on reset Soft = Soft reset
The connection memory of the TSI is accessible to switch connections.
9.5.2.1.1 TSI Connection Memory
Addresses
0x0 ... 0x3FFFC: TsiCnctMem0 ... TsiCnctMem65535
The lower 16bit value of TsiCnctMem cell 0 determines the input channel to which output
channel 0 is connected, the lower 16bit value of TsiCnctMem cell 1 determines the input
channel to which output channel 1 is connected, etc.
Setting Bit 16 results in discarding the output data of the TSI interchange data memory and
substituting it with the data in the lower 8 bit of this connection memory entry, e.g: Value
0x00001 at address 0x00005 connects TSI input channel 1 to output channel 5, value 0x10001
at address 0x00005 causes static idle pattern 0x01 to be output at channel 5.
Bit 17 of the Memory cells is read as written and has no influence on HW.