Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 208)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 208
9.5.2.5.3 Gr8 Control Register
Address:
0x1048, Gr8CtrlReg
Width: 32 bit
Enables Gr8 transmitter or receiver
9.5.2.6 TSI Interior/Exterior Test Pattern Generator Block (TsiTstPatGenBlk)
Resets:
Pwr = Power On Reset
Soft = Soft Reset
The TstPatGen generates a pseudo random binary sequence with the aid of a 11-bit LFSR
(feedback taps on stage nine and eleven). Alternatively a static pattern can be inserted.
In case of the Interior (Regs have indize 0) generator it substitutes the incoming data in a
timeslot to the TSI.
In case of the Exterior (Regs have indize 1) generator it substitutes an outgoing data of a
timeslot of the TSI.
Bit Acronym Type
Description
Default
Pwr Soft
31..
.2 - - reserved undef - -
1 Gr8RcvEnable RW 0b1: Gr8RcvEnable, enables reception
of Gr8 data
0b0: Gr8RcvDisable, no new data
arrives in the receive buffer 0b0 X X
0 Gr8TrmEnable RW 0b1: Gr8TrmEnable, enables
transimssion fo Gr8 data
0b0: Gr8TrmDisable, disables
transmission fo Gr8 data, normal Fs bits
are transmitted 000111000111... 0b0 X X