Figure 8-3, Spi flash configuration circuit, Base artm fpga – Artesyn ARTM-831X Installation and Use (June 2014) User Manual
Page 155
Base ARTM FPGA
ARTM-831X Installation and Use (6806800M76E)
155
A rising edge of the Signal FORCE_GOLDEN triggers a state machine implemented with FPGA
standard logic. The state machine sends SPI Flash commands to the FPGA Code SPI flash, which
corrupts the Working Image by erasing the first 4KB of the Working Image.
Note: This state machine needs to be implemented for all bitstream versions.
Note: This state machine is needed for all FPGA devices in the project.
Figure 8-3
SPI Flash Configuration circuit
FPGA Code SPI
Flash
ARTN Base FPGA
CONF_SPI_SCK
SCK
SS#
CONF_SPI_SS_
SI
CONF_SPI_MOSI
SO
CONF_SPI_MISO
WP#
CONF_SPI_SCK
CCLK
D[7]/SPID0
DI/CSSPI0N
D[0]/SPIFASTN
BUSY/SISPI
FORCE_GOLDEN
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