Ext fpga, 13xrt75 line interface line event mask register – Artesyn ARTM-831X Installation and Use (June 2014) User Manual
Page 322
EXT FPGA
ARTM-831X Installation and Use (6806800M76E)
322
10.4.2.1.13Xrt75 Line Interface Line Event Mask Register
Addresses:
0x38, Xrt75LineEvtMaskReg0
0x48, Xrt75LineEvtMaskReg1
0x58, Xrt75LineEvtMaskReg2
0x68, Xrt75LineEvtMaskReg3
Width: 32 bit
3
Xrt75RcvLoSIntrptReset3
RW
0b1:
Xrt75RcvLoSIntrptReset3,
resets Receiver Line 3
indicates loss of signal
indictor bit
0b0
X
X
2
Xrt75RcvLoSIntrptReset2
RW
0b1:
Xrt75RcvLoSIntrptReset2,
resets Receiver Line 2
indicates loss of signal
indictor bit
0b0
X
X
1
Xrt75RcvLoSIntrptReset1
RW
0b1:
Xrt75RcvLoSIntrptReset1,
resets Receiver Line 1
indicates loss of signal
indictor bit
0b0
X
X
0
Xrt75RcvLoSIntrptReset0
RW
0b1:
Xrt75RcvLoSIntrptReset0,
resets Receiver Line 0
indicates loss of signal
indictor bit
0b0
X
X
Bit
Acronym
Type
Description
Default
Pwr
Soft
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