Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 300)

EXT FPGA
ARTM-831X Installation and Use (6806800M76E) 300
10.4.2 EXT FPGA Registers Detailed Description
Keys:
Access types:
R = Read
W = Write
RW = Write and Read back exactly what was written last time
RorW = Write one value, eg. transmit data or read other value, eg. receive data
RandC = Read and Clear specified bits automatically
Default:
Binary(0b) or hex(0x) value the respective bits are set to, when one of the reset conditions in
the following columns occurs:
- = if nothing is stored, thus nothing can be reset
Framer and Line Interface Unit Sideband Signal Registers (FrLiuSdBndRegs) [Hw: Cy]
Registers to control, control further processing or monitor signals of XRT86-framers and XRT75 Line
interfaces
Access via Spi-bus 256Byte memory area, hereof assigned to this block: C0...FFF
Address Acronym Description
0xC0
0xC4 SelRclk2
SelRclk3 SelectRcvrdLclk (32bit) [Hw: syn, WAck1, RAck1]
The registers control which of 8 recovered line clocks from
XRT86 framer chips 2...5 or which of 6 recovered line clocks
from upto 4 line interfaces XRT75 is switched to the
respective ExtFpgaRLClk2 or ExtFpgaRLClk3 output of the
ExtFpga (SelRclk2 determines RtmExtFpgaRLClk2, SelRclk3
determines RtmExtFpgaRLClk3. The RtmExtFpgaRLClk2
and 3 are connected to the BaseExtFpga on the front board
which finally decides which RCLK to put for synchronization
to the central TDM clock generator. Dependent on the
module type not all clock sources may be present.
Table 10-4 EXT FPGA Addressmap Overview (continued)