Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 178)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 178
TSI Interior/Exterior Test Pattern Comparator Block (TsiTstPatCmpBlk) [Hw: Cy1, InR, OutR]
The TstPatCmp can be enabled to receive either static pattern or pseudo random pattern from a
remote generator.
In case of the Interior (Regs have indize 0) comparator it is connected to an outgoing timeslot of the
TSI.
In case of the Exterior (Regs have indize 1) comparator it is connected to an incoming timeslot into the
TSI.
The TSI timeslot is selectable between 0 and 65535.
The TstPatCmpBlk includes a PRBS pattern comparator (eleven stage LFSR with taps at the 9th and
11th stage).
The pattern comparator is able to synchronize itself to the receive bit stream. After synchronization
125 μs-frames and errors are counted.
A time of 125us delay has to be taken into account, till the comparator has stopped after resetting
TstPatCmpRxPatEn bit in TstPatCmpCtrlReg.
Access via PCI-bus 512kByte non-prefetchable memory area of 64bit-bar[3,2], hereof assigned to this
block: 10C0...10FF
Address Acronym Description
0x10C0
0x10E0 TstPatCmpTsReg0
TstPatCmpTsReg1 Test Pattern Comparator Timeslot Register (16bit) [Hw: asyn,
WAck4, RAck4]
This registers specify the outgoing (Int) or incoming (Ext) TSI
timeslot(0 ... 65535) to connect the comparator to.
0x10C2
0x10E2 TstPatRcvDatReg0
TstPatRcvDatReg1 Test Pattern Comparator Receive Data Register (8bit) [Hw: asyn
, WAck4, RAck4]
This registers holds the received pattern in the case of static
pattern reception. Not used in the case of pseudo random
pattern reception.
0x10C3
0x10E3 TstPatCmpDatReg0
TstPatCmpDatReg1 Test Pattern Comparator Data Register (8bit) [Hw: asyn, WAck4
, RAck4]
This registers holds the reference pattern in the case of static
pattern reception. Not used in the case of pseudo random
pattern reception.
Table 9-5 RTM FPGA Address map Overview (continued)