Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 204)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 204
9.5.2.4 TSI Registers (TsiRegs)
Resets:
Pwr = Power on reset
Soft = Soft reset
TSI Control and Status Registers to switch connections, initialize the connections by HW and
monitor initialization process, determine connection initialization value, determine data at Tsi
channel 0 input, monitor Tsi counter.
9.5.2.4.1 Tsi Initialization Register
Address:
0x1000, TsiInitReg
Width: 32 bit
The TsiCnctRegs are written with 0x0000 from TsiInitValReg during the first 250us after power-
on reset, thus connecting all output channels to input channel 0. All output channels carry then
as speech data the value from TsiCh0SpchDataReg (too 0x00 after power-on). The initialization
process can be monitored with TsiInitMonReg.
9.5.2.4.2 Tsi Initialization Monitor Register
Address:
0x1004, TsiInitMonReg
Width: 32 bit
Bit Acronym Type
Description
Default
Pwr Soft
31..
.16 - - reserved undef - -
15..
.0 TsiInitStart W 0xCEEC: TsiInitStart, Write 0xCEEC to
start Tsi initialization 0b0 F F