Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 257)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 257
9.5.2.11.26Spi 2 Bus Access Monitor Register
Address:
0x14B0, Spi2BusMonReg
Width: 8 bit
This register monitors the access to the local bus
9.5.2.11.27Spi 2 Bus Access Monitor Reset Register
Address:
0x14B1, Spi2BusMonResetReg
Width: 8 bit
This register resets the timeout flag in the respective monitor and address registers
9.5.2.11.28Spi 2 Bus Access Monitor Address Register
Address:
0x14B4, Spi2BusAccessTimeoutAddrReg
Width: 32 bit
Bit Acronym Type Description Default Pwr Soft
7...1 - - reserved undef - -
0 Spi2BusAccessTimeout R 0b1: Spi2BusAccessTimeout, An
access to the Spi2 bus timed out 0b0 F F
Bit Acronym Type Description Default Pwr Soft
7...1 - - reserved undef - -
0 Spi2BusAccessTimeoutReset RW 0b1:
Spi2BusAccessTimeoutR
eset, The timeout flag in
the monitor register is
reset. 0b0 X X