Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 174)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 174
Cell 0,4,8,... match to the SBI interface 0 (PMC8310 chip 0),
subsystem 0, channel 0,1,2,...
Cell 1,5,9, ... match to the SBI interface 0 (PMC8310 chip 0),
subsystem 1, channel 0,1,2,...
Cell 2,6,10, ... match to the SBI interface 0 (PMC8310 chip 0),
subsystem 2, channel 0,1,2,...
Cell 3,7,11, ... match to the SBI interface 0 (PMC8310 chip 0),
subsystem 3, channel 0,1,2,
...
Cell 336,340,344,... match to the SBI interface 1 (PMC8310
chip 1), subsystem 0, channel 0,1,2,
Cell 337,341,345, ... match to the SBI interface 1 (PMC8310
chip 1), subsystem 1, channel 0,1,2,
Cell 338,342,346, ... match to the SBI interface 1 (PMC8310
chip 1), subsystem 2, channel 0,1,2,
Cell 339,343,347, ... match to the SBI interface 1 (PMC8310
chip 1), subsystem 3, channel 0,1,2,
...
The cells 672,673 ... unused
...
The cells 768,769, ... 771 match to the T1 interface 0 (Xrt86
framer chip 0) channel 0,1,2,3,
The cells 772,773, ... 775 match to the T1 interface 0 (Xrt86
framer chip 0) channel 4,5,6,7,
...
The cells 816,817 ... 1023 unused
SerDes Client Interface (SerDesClientIf) [Hw: Cy1, InR, OutR]
Provides register access to the SerDes block
Access via PCI-bus 512kByte non-prefetchable memory area of 64bit-bar[3,2], hereof assigned to this
block: 0...FFF
Address Acronym Description
0x0
...
0x3F SerDesRegs SerDes Registers (8bit each)
Registerdescription Reg 0-63 see Handbook
Table 9-5 RTM FPGA Address map Overview (continued)