Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 324)

EXT FPGA
ARTM-831X Installation and Use (6806800M76E) 324
12 Xrt75RcvLoLIntrptMask4 RW 0b1:
Xrt75RcvLoLIntrptEnable4,
resets Receiver Line 4
indicates loss of lock
interrupt bit 0b0 X X
11 Xrt75RcvLoLIntrptMask3 RW 0b1:
Xrt75RcvLoLIntrptEnable3,
resets Receiver Line 3
indicates loss of lock
interrupt bit 0b0 X X
10 Xrt75RcvLoLIntrptMask2 RW 0b1:
Xrt75RcvLoLIntrptEnable2,
resets Receiver Line 2
indicates loss of lock
interrupt bit 0b0 X X
9 Xrt75RcvLoLIntrptMask1 RW 0b1:
Xrt75RcvLoLIntrptEnable1,
resets Receiver Line 1
indicates loss of lock
interrupt bit 0b0 X X
8 Xrt75RcvLoLIntrptMask0 RW 0b1:
Xrt75RcvLoLIntrptEnable0,
resets Receiver Line 0
indicates loss of lock
interrupt bit 0b0 X X
7...6 - - reserved undef - -
5 Xrt75RcvLoSIntrptMask5 RW 0b1:
Xrt75RcvLoSIntrptEnable5,
resets Receiver Line 5
indicates loss of signal
interrupt bit 0b0 X X
4 Xrt75RcvLoSIntrptMask4 RW 0b1:
Xrt75RcvLoSIntrptEnable4,
resets Receiver Line 4
indicates loss of signal
interrupt bit 0b0 X X
Bit Acronym Type Description Default Pwr Soft