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Tsi fpga – Artesyn ARTM-831X Installation and Use (June 2014) User Manual

Page 224

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TSI FPGA

ARTM-831X Installation and Use (6806800M76E)

224

This register indicates the number of 125 μs frames since starting the frame sync counting by
ErrCntCtrlReg:FrameCntStart bit. During 125 μs one SerDes frame is received. Each frame
contains a static test pattern and a CRC checksum.

Reg0 is for Serdes-connection to the BaseBoard, Reg1 to DMC1 and Reg2 to DMC2.

9.5.2.9.7 Deserializer Supplemental Test Pattern Error Count Register

Addresses:

0x120C, SupplTstPatErrCntReg0

0x124C, SupplTstPatErrCntReg1

0x128C, SupplTstPatErrCntReg2

Width: 32 bit

This register indicates the number of the test pattern errors since starting the static pattern
reception by the ErrCntCtrlReg:SupplTstPatErrCntStart bit. The counter sticks at 0xFFFF_FFFF.

Bit

Acronym

Type

Description
Default

Pwr

Soft

31..
.24

-

-

reserved

undef

-

-

23..
.0

TstFrameCnt

R

This bitfield indicates the time elapsed
since the start of frame counting by
setting the
ErrCntCtrlReg:FrameCntStart bit (value
x 125 μs). The counter sticks at
0xFFFFFF.

0x0

F

F