Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 329)

EXT FPGA
ARTM-831X Installation and Use (6806800M76E) 329
10.4.2.2.2 Configuration Prom Update Data Register
Address:
0x91, CfgPrmUpdDatReg
Width: 8 bit
Holds the write data to send to the FPGA serial configuration prom when written and the read
data received from the FPGA serial configuration prom when read.
10.4.2.3 General Test Registers (GenTestRegs)
Resets:
Pwr = Power on reset
Soft = Soft reset
General Test Registers
10.4.2.3.1 Fault Insertion Register
Address:
0xA0, FltInsrtReg
Width: 32 bit
Bit Acronym Type Description Default Pwr Soft
7...0 CfgSerialPrmDat RorW A write triggers 8 SPI clocks and shifts
the data out to MOSI. The Data on
MISO is shifted in. 0x0 X X