Tsi fpga – Artesyn ARTM-831X Installation and Use (June 2014) User Manual
Page 209
TSI FPGA
ARTM-831X Installation and Use (6806800M76E)
209
The TSI timeslot is selectable between 0 and 65535.
9.5.2.6.1 Test Pattern Generator Timeslot Register
Addresses:
0x1080, TstPatGenTsReg0
0x1090, TstPatGenTsReg1
Width: 16 bit
This registers specifies the incoming (Int) or outgoing (Ext) TSI timeslot (0 ... 65535) to be
substituted by generator pattern.
9.5.2.6.2 Test Pattern Generator Data Register
Addresses:
0x1082, TstPatGenDatReg0
0x1092, TstPatGenDatReg1
Width: 8 bit
This registers provides the test pattern to be transmitted in the case of static pattern
transmission.
Not used in the case of pseudo random pattern transmission.
Bit
Acronym
Type
Description
Default
Pwr
Soft
15..
.0
TstPatGenTsNo
RW
Selects the transmit timeslot
(0..65535)
0x0
X
X
Bit
Acronym
Type
Description
Default
Pwr
Soft
7...
0
TstPatGenData
RW
Static test pattern data
0x0
X
X
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