Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 205)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 205
The TsiCnctRegs are written with 0x0000 from TsiInitValReg during the first 250us after power-
on reset, thus connecting all output channels to input channel 0. All output channels carry then
as speech data the value from TsiCh0InpDatlReg (too 0x00 after power-on). This initialization
takes between 125 and 250us and can be monitored.
9.5.2.4.3 Tsi Initialization Value Register
Address:
0x1008, TsiInitValReg
Width: 32 bit
The TsiCnctRegs are written with the value of this register when initialization is started by
TsiInitReg
9.5.2.4.4 Tsi Channel 0 Input Data Register
Address:
0x100C, TsiCh0InpDatReg
Width: 32 bit
Bit Acronym Type
Description
Default
Pwr Soft
31..
.1 - - reserved undef - -
0 TsiInitDone R 0b1: TsiInitDone, Tsi initialization done
after power-on reset or initialization
restart by TsiInitReg, reset by power on
or when initialization is started by
TsiInitReg 0b0 F F
Bit Acronym Type
Description
Default
Pwr Soft
31..
.18 - - reserved undef - -
17..
.0 TsiInitValReg RW Value written to TsiCnctRegs during
initialization 0b0 X X